1. Field of the Invention
The present invention relates to an optical disc apparatus for recording information by forming a recording mark on a recording medium with a different physical property from that of the other portions of the medium.
2. Description of Related Art
With optical discs such as CDs and DVDs in widespread use, and with the development of the next-generation optical discs utilizing blue laser being well underway, there is a continuing demand for greater capacities. Optical disc products are now available that play back not just CDs but also DVDs and capable of recording a CD-R/RW, DVD-RAM, and DVD-R/RW on a single unit. Thus, there is also the need to improve the read/write compatibility for optical discs with different standards.
PRML (Partial Response Maximum Likelihood) is a widely used technique for increasing the capacity of magnetic discs, as it has an outstanding effect on improving S/N ratios. It continuously compares a read signal at time N and a target signal and binarizes the read signal into a most feasible bit sequence. Viterbi decoding, which is one of the ML schemes, is in wide practical use due to its ability to significantly reduce circuit size. Although a direct slice method has long been used as an optical disc read method, its limitations in achieving greater speed and capacity are obvious. Thus, PRML is also increasingly being applied as an optical disc read means.
In PRML, a target signal with a temporal transition that is closest to the read signal is selected, and the bit sequence that generates the target signal is outputted as the decoding result. The target signal is calculated by the convolution of a designated impulse response (PR class) and the bit sequence. Therefore, it is necessary to select an appropriate PR class depending on the recording density.
Meanwhile, modern optical disc apparatuses are being asked to be capable of recording and reading optical discs with different densities or formats.
For instance, in the case of Blu-ray Disc, products of recorders with recording capacity of 23.3 GB are now available, and it is expected that optical disc apparatuses accommodating 25 GB/27 GB will follow suit. These greater capacities are realized by improvements in terms of bits per inch, and capacities exceeding 30 GB are within reach in the future.
The following are more specific descriptions of the suitable PR class for the optical disc apparatuses of each generation accommodating each capacity of the Blu-ray Disc:    (1) First generation (accommodating 23.3 GB): PR(1,2,1)    (2) Second generation (accommodating 25 GB): PR(1,2,2,1)    (3) Third generation (accommodating 27 GB): PR(1,2,2,2,1)    (4) Fourth generation (accommodating 30 GB): PR(1,2,2,2,2,1)    (5) . . .
For instance, a third-generation optical disc apparatus is naturally desired to be capable of recording and reading media of 23.3 GB and 25 GB.
A technology to enable signals with different recording densities to be read using an optimum PR class is disclosed in JP Patent Publication (Kokai) No. 11-328860 A (1998) (corresponding to U.S. Pat. No. 6,333,907), whereby a plurality of Viterbi decoders are implemented and switched depending on recording density.
Another technology is disclosed in JP Patent Publication (Kokai) No. 10-106161 A (1998), whereby the tap coefficients of a FIR filter and a target level (recognition level) of a Viterbi decoder are determined as parameters based on a given value of inter-symbol interference of the read signal.
JP Patent Publication (Kokai) No. 10-334605 A (1998) discloses that different types of Viterbi decoding are implemented by switching the phase or the like when locking the PLL, such that a Viterbi decoding scheme more suitable for the characteristics of the read signal can be selected depending on the recording density.
Further, JP Patent Publication (Kokai) No. 11-296987 A (1999) discloses that the target signal level of a Viterbi decoder is caused to adaptively track the level of the read signal.
These technologies allow the Viterbi decoder to be physically or in effect switched for optimum read performance depending on the media with different recording densities.
Various technologies regarding the clock generation mechanism have also been disclosed which accommodate different recording densities.
FIG. 2 shows a diagram of a conventional PRML signal processing system. The PRML signal processing system operates with reference to a clock signal synchronized with the clock of the read signal, and so it employs a PLL (phase-locked loop) for synchronizing the clock of the signal processing system with the phase of the read signal. While there are a variety of PLL systems, when PLL is implemented following an ADC (analog-to-digital converter), as shown in FIG. 2, a digital PLL is generally employed that utilizes a digital phase comparator. Detailed description of the structure and operation of such PLL is omitted.
In a PLL, the phase comparator compares the phase between an input signal and a signal from its own VCO (voltage controlled oscillator). FIG. 3 shows the operational principle of a phase comparator of the 3-time scheme, where an n-time scheme means that values at n times including the current time at intervals T are used, T being the sampling interval in ADC, namely, the inverse of the clock frequency. Now, a read signal with no asymmetry and no direct-current offset is considered, and the central value of its envelope curve is defined as the reference signal level, namely, zero. In the case of the 3-time scheme, when the signs of x(n) and x(n−2) in a read signal sequence {x(n), x(n−1), x(n−2)} are different, this means that the O-level is being intersected in what is referred to as an “edge.” The value of x(n) is the value of the read signal sampled at time n. Similarly, in a 2-time scheme, the case where the signs of x(n) and x(n−1) are different indicates an edge. When the phase of the PLL and that of the input signal are completely aligned, the input signal prior to ADC is considered to intersect the 0-level at time (n−1)T, as shown in the drawing for the case with no phase difference. In that case, the values of time nT and (n−2)T of the edge signal sequence have the same absolute values with different signs. It is assumed in the illustrated example that these values were {−1, 0, 1}. If the phase of the clock signal were to advance, namely, if the phase of the input signal were to lag behind that of the clock signal by time ΔT, the input signal prior to ADC would have the trajectory indicated by the solid line in the figure. If this were to be sampled by ADC at each time, the absolute values at times nT and (n−2)T would be mutually different, or {−0.7, 0.3, 1.3} in the illustrated example. Conversely, by utilizing the value of each point of an edge, the phase difference between the read signal and the clock can be detected. By further determining whether the edge is a rise edge or a fall edge, a value φ proportional to the phase difference can be obtained. In the case of the 3-time scheme, the value φ can be obtained by the following equation, for example:Φ=Sgn(x(n)){x(n)+x(n−1)+x(n−2)}  (Eq. 1)
Similarly, for the 2-time scheme, the value can be determined by the following equation:Φ=Sgn(x(n)){x(n)+x(n−1)}  (Eq. 2)where
                              Sgn          ⁡                      (            x            )                          =                  {                                                                      1                  ⁢                                                                                                (                                      x                    >                    0                                    )                                                                                    0                                                              (                                      x                    =                    0                                    )                                                                                                                          -                    1                                    ⁢                                                                                                (                                      x                    <                    0                                    )                                                                                        (                  Eq          .                                          ⁢          3                )            The detection of an edge is carried out by monitoring the transition of the sign of the sampled value between the interval of the two or three times.
The aforementioned methods of detecting the phase difference have the problems that, if the recording density increases as mentioned above and if the amplitude (resolution) of a minimum run-length signal significantly decreases, the clock accuracy decreases or an accurate edge detection is prevented.
In order to solve the instability of the PLL caused by the decrease in the amplitude of the minimum run-length signal, a means for tentatively determining the sign can be inserted preceding the PLL, as disclosed in JP Patent Publication (Kokai) Nos. 2002-175673 A (corresponding to U.S. Patent Publication No. 2002-071194) and 10-172250 A (1998). It is also possible to carry out the phase detection at a target level other than the O-level, as disclosed in JP patent Publication (Kokai) No. 2000-182335 A.    Patent Document 1: JP Patent Publication (Kokai) No. 11-328860 A (1999)    Patent Document 2: JP Patent Publication (Kokai) No. 10-106161 A (1998)    Patent Document 3: JP Patent Publication (Kokai) No. 10-334605 A (1998)    Patent Document 4: JP Patent Publication (Kokai) No. 11-296987 A (1999)    Patent Document 5: JP Patent Publication (Kokai) No. 2002-175673 A    Patent Document 6: JP Patent Publication (Kokai) No. 10-172250 A (1998)    Patent Document 7: JP Patent Publication (Kokai) No. 2000-182335 A